sky130_fd_sc_ms__dlxbn

Delay latch, inverted enable, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ms__dlxbn

  • Type: cell

  • Verilog name: sky130_fd_sc_ms__dlxbn

  • Library: sky130_fd_sc_ms

  • Inputs: 2 (D, GATE_N)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_ms__dlxbn symbols

../../../../../_images/sky130_fd_sc_ms__dlxbn.symbol.svg
../../../../../_images/sky130_fd_sc_ms__dlxbn.pp.symbol.svg

sky130_fd_sc_ms__dlxbn schematic

../../../../../_images/sky130_fd_sc_ms__dlxbn.schematic.svg

sky130_fd_sc_ms__dlxbn GDSII layouts

../../../../../_images/sky130_fd_sc_ms__dlxbn_1.svg

sky130_fd_sc_ms__dlxbn_1

../../../../../_images/sky130_fd_sc_ms__dlxbn_2.svg

sky130_fd_sc_ms__dlxbn_2