SkyWater SKY130 PDK
Table Of Contents
SkyWater SKY130 PDK
Table Of Contents

Antenna Rules

Antenna rules specify the maximum allowed ratio of interconnect area exposed to plasma etch to active gate poly area that is electrically connected to it when the interconnect is etched. Interconnect areas exposed to plasma etch are:

  • bottom areas of Licon, Mcon, Via, Via2

  • perimeter areas of connection layers Poly, Li, Met1, Met2, Met3

Two types of checks are introduced in the following tables:

  • vertical for perimeter area, and

  • horizontal for contact area

The numbers checked for are in the MAX_EGAR column.

Definitions

Table 83 Antenna Rules Definitions

Symbol

Explanation

Unit

PI

Perimeter of Interconnect

um

FLT

Final Layer thickness

um

W

Width of MOS Transistor

um

L

Length of MOS Transistor

um

A

Area of MOS Transistor gate (= W x L)

um2

CA

Area of contact or via

um2

SW

Sidewall area (= PI x FLT)

um2

EA

Etched area (= CA for horizontal, = SW for vertical areas)

um2

Antenna rule numbers depend on the connection to the following devices:

pAntennaShort = (tap AndNot poly) AndNot nwell

It is a p+ tap contact used to shortcut to substrate ground buses.

AntennaDiode = (diff OR tap) AndNot (poly OR pAntennaShort)

It is a reverse biased diode whose leakage current will discharge the interconnect area.

These devices are not subject to LVS check and must not be reported in the schematic.

Antenna rules are defined for the following ratio:

When a diode is used

EGAR

Etch Gate Area Ratio = (EA / A_gate) - K x (AntennaDiode_area in um2) - diode_bonus [unitless]

When diodes are not used

EGAR

Etch Gate Area Ratio = (EA / A_gate) [unitless]

where:

  • K is a multiplying factor specified for each layer

  • AntennaDiode_area is the area of the AntennaDiode used to discharge the interconnect area exposed to plasma etch (should be 0 if no diode is used)

The layout should satisfy the condition: EGAR <= MAX_EGAR. The diode_bonus applies only when at least one diode is used, regardless from it’s size.

Tables

Todo

Most of these tables should be removed.

Table 84 Table Ia. Antenna rules (S8D*)

Antenna ratios

Area checked: H/V

FLT

MAX_EGAR

(ar_q.-.-)

Max EA/A w/o diode

K

Diode bonus

.poly.1

Poly (poly perimeter area/gate area)

Vertical

0.180

50

n/a

n/a

.licon.1

Licon (licon1 area/gate area)

Horizontal

3

n/a

n/a

.li.1

LI (LI perimeter area/gate area)

Vertical

0.100

75

450

n/a

.mcon.1

Mcon (mcon area/gate area)

Horizontal

3

18

n/a

.met1.1

Met1 (met1 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via.1

Via (via area/gate area)

Horizontal

6

36

n/a

.met2.1

Met2 (met2 perimeter area/gate area)

Vertical

0.350

400

400

2200

.pad.1

pad (via2 area/gate area)

Horizontal

6

36

n/a

.indm.1

INDM (met3 perimeter area/gate area)

Vertical

4.000

400

400

2200

.ar.1

Antenna rules not checked for features connected to a pAntennaShort

Design limitations due to antenna rules (FET gate = 1um2).

w/o diode

with 1um2 diode

Max length of Poly (approx, assumes min width)

135

n/a

Max number of Licons

103

n/a

Max length of LI (approx, assumes min width)

370

2620

Max number of Mcon

103

726

Max length of Met1 (approx, assumes min width)

570

4280

Max number of Via

266

1866

Max length of Met2 (approx, assumes min width)

570

4280

Max number of pad via

4

29

Max length of Met3 (approx, assumes min width)

45

370
Table 85 Table Ib. Antenna rules (S8TNV-5R)

Table Ib. Antenna rules (S8TNV-5R)

Antenna ratios

Area checked: H/V

FLT

MAX_EGAR

(ar_q.-.-)

Max EA/A w/o diode

K

Diode bonus

.poly.1

Poly (poly perimeter area/gate area)

Vertical

0.180

50

n/a

n/a

.licon.1

Licon (licon1 area/gate area)

Horizontal

3

n/a

n/a

.li.1

LI (LI perimeter area/gate area)

Vertical

0.100

75

450

n/a

.mcon.1

Mcon (mcon area/gate area)

Horizontal

3

18

n/a

.met1.1

Met1 (met1 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via.1

Via (via area/gate area)

Horizontal

6

36

n/a

.met2.1

Met2 (met2 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via2.1

Via2 (via2 area/gate area)

Horizontal

6

36

n/a

.met3.1

Met3 (met3 perimeter area/gate area)

Vertical

0.850

400

400

2200

.ar.1

Antenna rules not checked for features connected to a pAntennaShort

Design limitations due to antenna rules (FET gate = 1um2).

w/o diode

with 1um2 diode

Max length of Poly (approx, assumes min width)

135

n/a

Max number of Licons

103

n/a

Max length of LI (approx, assumes min width)

370

2620

Max number of Mcon

103

726

Max length of Met1 (approx, assumes min width)

570

4280

Max number of Via

266

1866

Max length of Met2 (approx, assumes min width)

570

4280

Max number of Via2

76

535

Max length of Met3 (approx, assumes min width)

230

1760
Table 86 Table Ic. Antenna rules (S8TM-5R*/S8TMC-5R*/S8TMA-5R*)

Table Ic. Antenna rules (S8TM-5R*/S8TMC-5R*/S8TMA-5R*)

Antenna ratios

Area checked: H/V

FLT

MAX_EGAR

(ar_q.-.-)

Max EA/A w/o diode

K

Diode bonus

.poly.1

Poly (poly perimeter area/gate area)

Vertical

0.180

50

n/a

n/a

.licon.1

Licon (licon1 area/gate area)

Horizontal

3

n/a

n/a

.li.1

LI (LI perimeter area/gate area)

Vertical

0.100

75

450

n/a

.mcon.1

Mcon (mcon area/gate area)

Horizontal

3

18

n/a

.met1.1

Met1 (met1 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via.1

Via (via area/gate area)

Horizontal

6

36

n/a

.met2.1

Met2 (met2 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via2.1

Via2 (via2 area/gate area)

Horizontal

6

36

n/a

.met3.1

Met3 (met3 perimeter area/gate area)

Vertical

2.000

400

400

2200

.ar.1

Antenna rules not checked for features connected to a pAntennaShort

Design limitations due to antenna rules (FET gate = 1um2).

w/o diode

with 1um2 diode

Max length of Poly (approx, assumes min width)

135

n/a

Max number of Licons

103

n/a

Max length of LI (approx, assumes min width)

370

2620

Max number of Mcon

103

726

Max length of Met1 (approx, assumes min width)

570

4280

Max number of Via

266

1866

Max length of Met2 (approx, assumes min width)

570

4280

Max number of Via2

9

65

Max length of Met3 (approx, assumes min width)

95

740
Table 87 Table Ie. Antenna rules (S8P-5R/SP8P-5R/S8P-10R*)

Table Ie. Antenna rules (S8P-5R/SP8P-5R/S8P-10R*)

Antenna ratios

Area checked: H/V

FLT

MAX_EGAR

(ar_q.-.-)

Max EA/A w/o diode

K

Diode bonus

.poly.1

Poly (poly perimeter area/gate area)

Vertical

0.180

50

n/a

n/a

.licon.1

Licon (licon1 area/gate area)

Horizontal

3

n/a

n/a

.li.1

LI (LI perimeter area/gate area)

Vertical

0.100

75

450

n/a

.mcon.1

Mcon (mcon area/gate area)

Horizontal

3

18

n/a

.met1.1

Met1 (met1 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via.1

Via (via area/gate area)

Horizontal

6

36

n/a

.met2.1

Met2 (met2 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via2.1

Via2 (via2 area/gate area)

Horizontal

6

36

n/a

.met3.1

Met3 (met3 perimeter area/gate area)

Vertical

0.800

400

400

2200

via3.1

Via3 (via3 area/gate area)

Horizontal

6

36

n/a

met4.1

Met4 (met4 perimeter area/gate area)

Vertical

0.800

400

400

2200

via4.1

Via3 (via3 area/gate area)

Horizontal

6

36

n/a

waffle_chip

Met4 (met4 perimeter area/gate area)

Vertical

2.000

400

400

2200

.ar.1

Antenna rules not checked for features connected to a pAntennaShort

Design limitations due to antenna rules (FET gate = 1um2).

w/o diode

with 1um2 diode

Max length of Poly (approx, assumes min width)

135

n/a

Max number of Licons

103

n/a

Max length of LI (approx, assumes min width)

370

2620

Max number of Mcon

103

726

Max length of Met1 (approx, assumes min width)

570

4280

Max number of Via

266

1866

Max length of Met2 (approx, assumes min width)

570

4280

Max number of Via2

150

1050

Max length of Met3 (approx, assumes min width)

245

1870

Max number of Via3

150

1050

Max length of Met4 (approx, assumes min width)

245

1870

Max number of Via4

9

65

Max length of Met5 (approx, assumes min width)

95

740
Table 88 Table Ig. Antenna rules (S8P12-10R*/S8PIR-10R/S8PF-10R*)

Table Ig. Antenna rules (S8P12-10R*/S8PIR-10R/S8PF-10R*)

Antenna ratios

Area checked: H/V

FLT

MAX_EGAR

(ar_q.-.-)

Max EA/A w/o diode

K

Diode bonus

.poly.1

Poly (poly perimeter area/gate area)

Vertical

0.180

50

n/a

n/a

.licon.1

Licon (licon1 area/gate area)

Horizontal

3

n/a

n/a

.li.1

LI (LI perimeter area/gate area)

Vertical

0.100

75

450

n/a

.mcon.1

Mcon (mcon area/gate area)

Horizontal

3

18

n/a

.met1.1

Met1 (met1 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via.1

Via (via area/gate area)

Horizontal

6

36

n/a

.met2.1

Met2 (met2 perimeter area/gate area)

Vertical

0.350

400

400

2200

.via2.1

Via2 (via2 area/gate area)

Horizontal

6

36

n/a

.met3.1

Met3 (met3 perimeter area/gate area)

Vertical

0.800

400

400

2200

via3.1

Via3 (via3 area/gate area)

Horizontal

6

36

n/a

met4.1

Met4 (met4 perimeter area/gate area)

Vertical

0.800

400

400

2200

via4.1

Via3 (via3 area/gate area)

Horizontal

6

36

n/a

met5.1

Met4 (met4 perimeter area/gate area)

Vertical

1.200

400

400

2200

.ar.1

Antenna rules not checked for features connected to a pAntennaShort

Design limitations due to antenna rules (FET gate = 1um2).

w/o diode

with 1um2 diode

Max length of Poly (approx, assumes min width)

135

n/a

Max number of Licons

103

n/a

Max length of LI (approx, assumes min width)

370

2620

Max number of Mcon

103

726

Max length of Met1 (approx, assumes min width)

570

4280

Max number of Via

266

1866

Max length of Met2 (approx, assumes min width)

570

4280

Max number of Via2

150

1050

Max length of Met3 (approx, assumes min width)

245

1870

Max number of Via3

150

1050

Max length of Met4 (approx, assumes min width)

245

1870

Max number of Via4

9

65

Max length of Met5 (approx, assumes min width)

165

1240

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