sky130_fd_sc_ms__dfsbp

Delay flop, inverted set, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ms__dfsbp

  • Type: cell

  • Verilog name: sky130_fd_sc_ms__dfsbp

  • Library: sky130_fd_sc_ms

  • Inputs: 3 (CLK, D, SET_B)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_ms__dfsbp symbols

../../../../../_images/sky130_fd_sc_ms__dfsbp.symbol.svg
../../../../../_images/sky130_fd_sc_ms__dfsbp.pp.symbol.svg

sky130_fd_sc_ms__dfsbp schematic

../../../../../_images/sky130_fd_sc_ms__dfsbp.schematic.svg

sky130_fd_sc_ms__dfsbp GDSII layouts

../../../../../_images/sky130_fd_sc_ms__dfsbp_1.svg

sky130_fd_sc_ms__dfsbp_1

../../../../../_images/sky130_fd_sc_ms__dfsbp_2.svg

sky130_fd_sc_ms__dfsbp_2