sky130_fd_sc_ms__clkdlyinv3sd1

Clock Delay Inverter 3-stage 0.15um length inner stage gate

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ms__clkdlyinv3sd1

  • Type: cell

  • Verilog name: sky130_fd_sc_ms__clkdlyinv3sd1

  • Library: sky130_fd_sc_ms

  • Inputs: 1 (A)

  • Outputs: 1 (Y)

sky130_fd_sc_ms__clkdlyinv3sd1 symbols

../../../../../_images/sky130_fd_sc_ms__clkdlyinv3sd1.symbol.svg
../../../../../_images/sky130_fd_sc_ms__clkdlyinv3sd1.pp.symbol.svg

sky130_fd_sc_ms__clkdlyinv3sd1 schematic

../../../../../_images/sky130_fd_sc_ms__clkdlyinv3sd1.schematic.svg

sky130_fd_sc_ms__clkdlyinv3sd1 GDSII layouts

../../../../../_images/sky130_fd_sc_ms__clkdlyinv3sd1_1.svg

sky130_fd_sc_ms__clkdlyinv3sd1_1