sky130_fd_sc_ls__dfsbp¶
Delay flop, inverted set, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_ls__dfsbp
Type: cell
Verilog name: sky130_fd_sc_ls__dfsbp
Library: sky130_fd_sc_ls
Inputs: 3 (CLK, D, SET_B)
Outputs: 2 (Q, Q_N)
sky130_fd_sc_ls__dfsbp symbols¶
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sky130_fd_sc_ls__dfsbp schematic¶
sky130_fd_sc_ls__dfsbp GDSII layouts¶
sky130_fd_sc_ls__dfsbp_1¶
sky130_fd_sc_ls__dfsbp_2¶