sky130_fd_sc_ls__dfbbn

Delay flop, inverted set, inverted reset, inverted clock, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ls__dfbbn

  • Type: cell

  • Verilog name: sky130_fd_sc_ls__dfbbn

  • Library: sky130_fd_sc_ls

  • Inputs: 4 (D, CLK_N, SET_B, RESET_B)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_ls__dfbbn symbols

../../../../../_images/sky130_fd_sc_ls__dfbbn.symbol.svg
../../../../../_images/sky130_fd_sc_ls__dfbbn.pp.symbol.svg

sky130_fd_sc_ls__dfbbn schematic

../../../../../_images/sky130_fd_sc_ls__dfbbn.schematic.svg

sky130_fd_sc_ls__dfbbn GDSII layouts

../../../../../_images/sky130_fd_sc_ls__dfbbn_1.svg

sky130_fd_sc_ls__dfbbn_1

../../../../../_images/sky130_fd_sc_ls__dfbbn_2.svg

sky130_fd_sc_ls__dfbbn_2