sky130_fd_sc_ls__clkdlyinv3sd2¶
Clock Delay Inverter 3-stage 0.25um length inner stage gate
This is a stub of cell description file
Cell name: sky130_fd_sc_ls__clkdlyinv3sd2
Type: cell
Verilog name: sky130_fd_sc_ls__clkdlyinv3sd2
Library: sky130_fd_sc_ls
Inputs: 1 (A)
Outputs: 1 (Y)
sky130_fd_sc_ls__clkdlyinv3sd2 symbols¶
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sky130_fd_sc_ls__clkdlyinv3sd2 schematic¶
sky130_fd_sc_ls__clkdlyinv3sd2 GDSII layouts¶
sky130_fd_sc_ls__clkdlyinv3sd2_1¶