sky130_fd_sc_hs__sedfxtp¶
Scan delay flop, data enable, non-inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__sedfxtp
Type: cell
Verilog name: sky130_fd_sc_hs__sedfxtp
Library: sky130_fd_sc_hs
Inputs: 5 (CLK, D, DE, SCD, SCE)
Outputs: 1 (Q)
sky130_fd_sc_hs__sedfxtp symbols¶
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sky130_fd_sc_hs__sedfxtp schematic¶
sky130_fd_sc_hs__sedfxtp GDSII layouts¶
sky130_fd_sc_hs__sedfxtp_1¶
sky130_fd_sc_hs__sedfxtp_2¶
sky130_fd_sc_hs__sedfxtp_4¶