sky130_fd_sc_hs__sdfsbp¶
Scan delay flop, inverted set, non-inverted clock, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__sdfsbp
Type: cell
Verilog name: sky130_fd_sc_hs__sdfsbp
Library: sky130_fd_sc_hs
Inputs: 5 (CLK, D, SCD, SCE, SET_B)
Outputs: 2 (Q, Q_N)
sky130_fd_sc_hs__sdfsbp symbols¶
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sky130_fd_sc_hs__sdfsbp schematic¶
sky130_fd_sc_hs__sdfsbp GDSII layouts¶
sky130_fd_sc_hs__sdfsbp_1¶
sky130_fd_sc_hs__sdfsbp_2¶