sky130_fd_sc_hs__dlxtn

Delay latch, inverted enable, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__dlxtn

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__dlxtn

  • Library: sky130_fd_sc_hs

  • Inputs: 2 (D, GATE_N)

  • Outputs: 1 (Q)

sky130_fd_sc_hs__dlxtn symbols

../../../../../_images/sky130_fd_sc_hs__dlxtn.symbol.svg
../../../../../_images/sky130_fd_sc_hs__dlxtn.pp.symbol.svg

sky130_fd_sc_hs__dlxtn schematic

../libraries/sky130_fd_sc_hs/latest/cells/dlxtn/sky130_fd_sc_hs__dlxtn.schematic.svg

sky130_fd_sc_hs__dlxtn GDSII layouts

../../../../../_images/sky130_fd_sc_hs__dlxtn_1.svg

sky130_fd_sc_hs__dlxtn_1

../../../../../_images/sky130_fd_sc_hs__dlxtn_2.svg

sky130_fd_sc_hs__dlxtn_2

../../../../../_images/sky130_fd_sc_hs__dlxtn_4.svg

sky130_fd_sc_hs__dlxtn_4