sky130_fd_sc_hs__dlrbn

Delay latch, inverted reset, inverted enable, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__dlrbn

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__dlrbn

  • Library: sky130_fd_sc_hs

  • Inputs: 3 (RESET_B, D, GATE_N)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_hs__dlrbn symbols

../../../../../_images/sky130_fd_sc_hs__dlrbn.symbol.svg
../../../../../_images/sky130_fd_sc_hs__dlrbn.pp.symbol.svg

sky130_fd_sc_hs__dlrbn schematic

../libraries/sky130_fd_sc_hs/latest/cells/dlrbn/sky130_fd_sc_hs__dlrbn.schematic.svg

sky130_fd_sc_hs__dlrbn GDSII layouts

../../../../../_images/sky130_fd_sc_hs__dlrbn_1.svg

sky130_fd_sc_hs__dlrbn_1

../../../../../_images/sky130_fd_sc_hs__dlrbn_2.svg

sky130_fd_sc_hs__dlrbn_2