sky130_fd_sc_hs__dlclkp

Clock gate

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__dlclkp

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__dlclkp

  • Library: sky130_fd_sc_hs

  • Inputs: 2 (GATE, CLK)

  • Outputs: 1 (GCLK)

sky130_fd_sc_hs__dlclkp symbols

../../../../../_images/sky130_fd_sc_hs__dlclkp.symbol.svg
../../../../../_images/sky130_fd_sc_hs__dlclkp.pp.symbol.svg

sky130_fd_sc_hs__dlclkp schematic

../libraries/sky130_fd_sc_hs/latest/cells/dlclkp/sky130_fd_sc_hs__dlclkp.schematic.svg

sky130_fd_sc_hs__dlclkp GDSII layouts

../../../../../_images/sky130_fd_sc_hs__dlclkp_1.svg

sky130_fd_sc_hs__dlclkp_1

../../../../../_images/sky130_fd_sc_hs__dlclkp_2.svg

sky130_fd_sc_hs__dlclkp_2

../../../../../_images/sky130_fd_sc_hs__dlclkp_4.svg

sky130_fd_sc_hs__dlclkp_4