sky130_fd_sc_hs__dfrtp¶
Delay flop, inverted reset, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__dfrtp
Type: cell
Verilog name: sky130_fd_sc_hs__dfrtp
Library: sky130_fd_sc_hs
Inputs: 3 (RESET_B, CLK, D)
Outputs: 1 (Q)
sky130_fd_sc_hs__dfrtp symbols¶
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sky130_fd_sc_hs__dfrtp schematic¶
sky130_fd_sc_hs__dfrtp GDSII layouts¶
sky130_fd_sc_hs__dfrtp_1¶
sky130_fd_sc_hs__dfrtp_2¶
sky130_fd_sc_hs__dfrtp_4¶