sky130_fd_sc_hs__dfrtn¶
Delay flop, inverted reset, inverted clock, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__dfrtn
Type: cell
Verilog name: sky130_fd_sc_hs__dfrtn
Library: sky130_fd_sc_hs
Inputs: 3 (RESET_B, CLK_N, D)
Outputs: 1 (Q)
sky130_fd_sc_hs__dfrtn symbols¶
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sky130_fd_sc_hs__dfrtn schematic¶
sky130_fd_sc_hs__dfrtn GDSII layouts¶
sky130_fd_sc_hs__dfrtn_1¶