sky130_fd_sc_hs__clkdlyinv5sd3¶
Clock Delay Inverter 5-stage 0.50um length inner stage gate
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__clkdlyinv5sd3
Type: cell
Verilog name: sky130_fd_sc_hs__clkdlyinv5sd3
Library: sky130_fd_sc_hs
Inputs: 1 (A)
Outputs: 1 (Y)
sky130_fd_sc_hs__clkdlyinv5sd3 symbols¶
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sky130_fd_sc_hs__clkdlyinv5sd3 schematic¶
sky130_fd_sc_hs__clkdlyinv5sd3 GDSII layouts¶
sky130_fd_sc_hs__clkdlyinv5sd3_1¶