sky130_fd_sc_hs__clkdlyinv5sd2

Clock Delay Inverter 5-stage 0.25um length inner stage gate

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__clkdlyinv5sd2

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__clkdlyinv5sd2

  • Library: sky130_fd_sc_hs

  • Inputs: 1 (A)

  • Outputs: 1 (Y)

sky130_fd_sc_hs__clkdlyinv5sd2 symbols

../../../../../_images/sky130_fd_sc_hs__clkdlyinv5sd2.symbol.svg
../../../../../_images/sky130_fd_sc_hs__clkdlyinv5sd2.pp.symbol.svg

sky130_fd_sc_hs__clkdlyinv5sd2 schematic

../libraries/sky130_fd_sc_hs/latest/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2.schematic.svg

sky130_fd_sc_hs__clkdlyinv5sd2 GDSII layouts

../../../../../_images/sky130_fd_sc_hs__clkdlyinv5sd2_1.svg

sky130_fd_sc_hs__clkdlyinv5sd2_1