sky130_fd_sc_hdll__sedfxbp

Scan delay flop, data enable, non-inverted clock, complementary outputs

This is a stub of cell description file

• Cell name: sky130_fd_sc_hdll__sedfxbp

• Type: cell

• Verilog name: sky130_fd_sc_hdll__sedfxbp

• Library: sky130_fd_sc_hdll

• Inputs: 5 (CLK, D, DE, SCD, SCE)

• Outputs: 2 (Q, Q_N)

sky130_fd_sc_hdll__sedfxbp symbols

sky130_fd_sc_hdll__sedfxbp schematic

sky130_fd_sc_hdll__sedfxbp GDSII layouts

sky130_fd_sc_hdll__sedfxbp_1

sky130_fd_sc_hdll__sedfxbp_2