sky130_fd_sc_hdll__sdlclkp

Scan gated clock

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__sdlclkp

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__sdlclkp

  • Library: sky130_fd_sc_hdll

  • Inputs: 3 (SCE, GATE, CLK)

  • Outputs: 1 (GCLK)

sky130_fd_sc_hdll__sdlclkp symbols

../../../../../_images/sky130_fd_sc_hdll__sdlclkp.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__sdlclkp.pp.symbol.svg

sky130_fd_sc_hdll__sdlclkp schematic

../../../../../_images/sky130_fd_sc_hdll__sdlclkp.schematic.svg

sky130_fd_sc_hdll__sdlclkp GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__sdlclkp_1.svg

sky130_fd_sc_hdll__sdlclkp_1

../../../../../_images/sky130_fd_sc_hdll__sdlclkp_2.svg

sky130_fd_sc_hdll__sdlclkp_2

../../../../../_images/sky130_fd_sc_hdll__sdlclkp_4.svg

sky130_fd_sc_hdll__sdlclkp_4