sky130_fd_sc_hdll__or2b

2-input OR, first input inverted

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__or2b

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__or2b

  • Library: sky130_fd_sc_hdll

  • Inputs: 2 (A, B_N)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__or2b symbols

../../../../../_images/sky130_fd_sc_hdll__or2b.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__or2b.pp.symbol.svg

sky130_fd_sc_hdll__or2b schematic

../../../../../_images/sky130_fd_sc_hdll__or2b.schematic.svg

sky130_fd_sc_hdll__or2b GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__or2b_1.svg

sky130_fd_sc_hdll__or2b_1

../../../../../_images/sky130_fd_sc_hdll__or2b_2.svg

sky130_fd_sc_hdll__or2b_2

../../../../../_images/sky130_fd_sc_hdll__or2b_4.svg

sky130_fd_sc_hdll__or2b_4