sky130_fd_sc_hdll__inv

Inverter

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__inv

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__inv

  • Library: sky130_fd_sc_hdll

  • Inputs: 1 (A)

  • Outputs: 1 (Y)

sky130_fd_sc_hdll__inv symbols

../../../../../_images/sky130_fd_sc_hdll__inv.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__inv.pp.symbol.svg

sky130_fd_sc_hdll__inv schematic

../../../../../_images/sky130_fd_sc_hdll__inv.schematic.svg

sky130_fd_sc_hdll__inv GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__inv_1.svg

sky130_fd_sc_hdll__inv_1

../../../../../_images/sky130_fd_sc_hdll__inv_12.svg

sky130_fd_sc_hdll__inv_12

../../../../../_images/sky130_fd_sc_hdll__inv_16.svg

sky130_fd_sc_hdll__inv_16

../../../../../_images/sky130_fd_sc_hdll__inv_2.svg

sky130_fd_sc_hdll__inv_2

../../../../../_images/sky130_fd_sc_hdll__inv_4.svg

sky130_fd_sc_hdll__inv_4

../../../../../_images/sky130_fd_sc_hdll__inv_6.svg

sky130_fd_sc_hdll__inv_6

../../../../../_images/sky130_fd_sc_hdll__inv_8.svg

sky130_fd_sc_hdll__inv_8