sky130_fd_sc_hdll__clkmux2

Clock mux

This is a stub of cell description file

• Cell name: sky130_fd_sc_hdll__clkmux2

• Type: cell

• Verilog name: sky130_fd_sc_hdll__clkmux2

• Library: sky130_fd_sc_hdll

• Inputs: 3 (A0, A1, S)

• Outputs: 1 (X)

sky130_fd_sc_hdll__clkmux2 symbols

sky130_fd_sc_hdll__clkmux2 schematic

sky130_fd_sc_hdll__clkmux2 GDSII layouts

sky130_fd_sc_hdll__clkmux2_1

sky130_fd_sc_hdll__clkmux2_2

sky130_fd_sc_hdll__clkmux2_4