sky130_fd_sc_hdll__clkinvlp

Lower power Clock tree inverter

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__clkinvlp

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__clkinvlp

  • Library: sky130_fd_sc_hdll

  • Inputs: 1 (A)

  • Outputs: 1 (Y)

sky130_fd_sc_hdll__clkinvlp symbols

../../../../../_images/sky130_fd_sc_hdll__clkinvlp.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__clkinvlp.pp.symbol.svg

sky130_fd_sc_hdll__clkinvlp schematic

../../../../../_images/sky130_fd_sc_hdll__clkinvlp.schematic.svg

sky130_fd_sc_hdll__clkinvlp GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__clkinvlp_2.svg

sky130_fd_sc_hdll__clkinvlp_2

../../../../../_images/sky130_fd_sc_hdll__clkinvlp_4.svg

sky130_fd_sc_hdll__clkinvlp_4