sky130_fd_sc_hdll__clkinv

Clock tree inverter

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__clkinv

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__clkinv

  • Library: sky130_fd_sc_hdll

  • Inputs: 1 (A)

  • Outputs: 1 (Y)

sky130_fd_sc_hdll__clkinv symbols

../../../../../_images/sky130_fd_sc_hdll__clkinv.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__clkinv.pp.symbol.svg

sky130_fd_sc_hdll__clkinv schematic

../../../../../_images/sky130_fd_sc_hdll__clkinv.schematic.svg

sky130_fd_sc_hdll__clkinv GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__clkinv_1.svg

sky130_fd_sc_hdll__clkinv_1

../../../../../_images/sky130_fd_sc_hdll__clkinv_12.svg

sky130_fd_sc_hdll__clkinv_12

../../../../../_images/sky130_fd_sc_hdll__clkinv_16.svg

sky130_fd_sc_hdll__clkinv_16

../../../../../_images/sky130_fd_sc_hdll__clkinv_2.svg

sky130_fd_sc_hdll__clkinv_2

../../../../../_images/sky130_fd_sc_hdll__clkinv_4.svg

sky130_fd_sc_hdll__clkinv_4

../../../../../_images/sky130_fd_sc_hdll__clkinv_8.svg

sky130_fd_sc_hdll__clkinv_8