sky130_fd_sc_hdll__clkbuf

Clock tree buffer

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__clkbuf

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__clkbuf

  • Library: sky130_fd_sc_hdll

  • Inputs: 1 (A)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__clkbuf symbols

../../../../../_images/sky130_fd_sc_hdll__clkbuf.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__clkbuf.pp.symbol.svg

sky130_fd_sc_hdll__clkbuf schematic

../../../../../_images/sky130_fd_sc_hdll__clkbuf.schematic.svg

sky130_fd_sc_hdll__clkbuf GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__clkbuf_1.svg

sky130_fd_sc_hdll__clkbuf_1

../../../../../_images/sky130_fd_sc_hdll__clkbuf_12.svg

sky130_fd_sc_hdll__clkbuf_12

../../../../../_images/sky130_fd_sc_hdll__clkbuf_16.svg

sky130_fd_sc_hdll__clkbuf_16

../../../../../_images/sky130_fd_sc_hdll__clkbuf_2.svg

sky130_fd_sc_hdll__clkbuf_2

../../../../../_images/sky130_fd_sc_hdll__clkbuf_4.svg

sky130_fd_sc_hdll__clkbuf_4

../../../../../_images/sky130_fd_sc_hdll__clkbuf_6.svg

sky130_fd_sc_hdll__clkbuf_6

../../../../../_images/sky130_fd_sc_hdll__clkbuf_8.svg

sky130_fd_sc_hdll__clkbuf_8