sky130_fd_sc_hdll__buf

Buffer

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__buf

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__buf

  • Library: sky130_fd_sc_hdll

  • Inputs: 1 (A)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__buf symbols

../../../../../_images/sky130_fd_sc_hdll__buf.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__buf.pp.symbol.svg

sky130_fd_sc_hdll__buf schematic

../../../../../_images/sky130_fd_sc_hdll__buf.schematic.svg

sky130_fd_sc_hdll__buf GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__buf_1.svg

sky130_fd_sc_hdll__buf_1

../../../../../_images/sky130_fd_sc_hdll__buf_12.svg

sky130_fd_sc_hdll__buf_12

../../../../../_images/sky130_fd_sc_hdll__buf_16.svg

sky130_fd_sc_hdll__buf_16

../../../../../_images/sky130_fd_sc_hdll__buf_2.svg

sky130_fd_sc_hdll__buf_2

../../../../../_images/sky130_fd_sc_hdll__buf_4.svg

sky130_fd_sc_hdll__buf_4

../../../../../_images/sky130_fd_sc_hdll__buf_6.svg

sky130_fd_sc_hdll__buf_6

../../../../../_images/sky130_fd_sc_hdll__buf_8.svg

sky130_fd_sc_hdll__buf_8