sky130_fd_sc_hd__lpflow_clkbufkapwr

Clock tree buffer on keep-alive power rail

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__lpflow_clkbufkapwr

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__lpflow_clkbufkapwr

  • Library: sky130_fd_sc_hd

  • Inputs: 1 (A)

  • Outputs: 1 (X)

sky130_fd_sc_hd__lpflow_clkbufkapwr symbols

../../../../../_images/sky130_fd_sc_hd__lpflow_clkbufkapwr.symbol.svg
../../../../../_images/sky130_fd_sc_hd__lpflow_clkbufkapwr.pp.symbol.svg

sky130_fd_sc_hd__lpflow_clkbufkapwr schematic

../../../../../_images/sky130_fd_sc_hd__lpflow_clkbufkapwr.schematic.svg

sky130_fd_sc_hd__lpflow_clkbufkapwr GDSII layouts

../../../../../_images/sky130_fd_sc_hd__lpflow_clkbufkapwr_1.svg

sky130_fd_sc_hd__lpflow_clkbufkapwr_1

../../../../../_images/sky130_fd_sc_hd__lpflow_clkbufkapwr_16.svg

sky130_fd_sc_hd__lpflow_clkbufkapwr_16

../../../../../_images/sky130_fd_sc_hd__lpflow_clkbufkapwr_2.svg

sky130_fd_sc_hd__lpflow_clkbufkapwr_2

../../../../../_images/sky130_fd_sc_hd__lpflow_clkbufkapwr_4.svg

sky130_fd_sc_hd__lpflow_clkbufkapwr_4

../../../../../_images/sky130_fd_sc_hd__lpflow_clkbufkapwr_8.svg

sky130_fd_sc_hd__lpflow_clkbufkapwr_8