sky130_fd_sc_hd__dfxbp

Delay flop, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__dfxbp

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__dfxbp

  • Library: sky130_fd_sc_hd

  • Inputs: 2 (CLK, D)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_hd__dfxbp symbols

../../../../../_images/sky130_fd_sc_hd__dfxbp.symbol.svg
../../../../../_images/sky130_fd_sc_hd__dfxbp.pp.symbol.svg

sky130_fd_sc_hd__dfxbp schematic

../../../../../_images/sky130_fd_sc_hd__dfxbp.schematic.svg

sky130_fd_sc_hd__dfxbp GDSII layouts

../../../../../_images/sky130_fd_sc_hd__dfxbp_1.svg

sky130_fd_sc_hd__dfxbp_1

../../../../../_images/sky130_fd_sc_hd__dfxbp_2.svg

sky130_fd_sc_hd__dfxbp_2