sky130_fd_sc_hd__dfstp¶
Delay flop, inverted set, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__dfstp
Type: cell
Verilog name: sky130_fd_sc_hd__dfstp
Library: sky130_fd_sc_hd
Inputs: 3 (CLK, D, SET_B)
Outputs: 1 (Q)
sky130_fd_sc_hd__dfstp symbols¶
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sky130_fd_sc_hd__dfstp schematic¶
sky130_fd_sc_hd__dfstp GDSII layouts¶
sky130_fd_sc_hd__dfstp_1¶
sky130_fd_sc_hd__dfstp_2¶
sky130_fd_sc_hd__dfstp_4¶