sky130_fd_sc_hd__dfrtp

Delay flop, inverted reset, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__dfrtp

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__dfrtp

  • Library: sky130_fd_sc_hd

  • Inputs: 3 (CLK, D, RESET_B)

  • Outputs: 1 (Q)

sky130_fd_sc_hd__dfrtp symbols

../../../../../_images/sky130_fd_sc_hd__dfrtp.symbol.svg
../../../../../_images/sky130_fd_sc_hd__dfrtp.pp.symbol.svg

sky130_fd_sc_hd__dfrtp schematic

../../../../../_images/sky130_fd_sc_hd__dfrtp.schematic.svg

sky130_fd_sc_hd__dfrtp GDSII layouts

../../../../../_images/sky130_fd_sc_hd__dfrtp_1.svg

sky130_fd_sc_hd__dfrtp_1

../../../../../_images/sky130_fd_sc_hd__dfrtp_2.svg

sky130_fd_sc_hd__dfrtp_2

../../../../../_images/sky130_fd_sc_hd__dfrtp_4.svg

sky130_fd_sc_hd__dfrtp_4