sky130_fd_sc_hd__clkdlybuf4s50¶
Clock Delay Buffer 4-stage 0.59um length inner stage gates
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__clkdlybuf4s50
Type: cell
Verilog name: sky130_fd_sc_hd__clkdlybuf4s50
Library: sky130_fd_sc_hd
Inputs: 1 (A)
Outputs: 1 (X)
sky130_fd_sc_hd__clkdlybuf4s50 symbols¶
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sky130_fd_sc_hd__clkdlybuf4s50 schematic¶
sky130_fd_sc_hd__clkdlybuf4s50 GDSII layouts¶
sky130_fd_sc_hd__clkdlybuf4s50_1¶
sky130_fd_sc_hd__clkdlybuf4s50_2¶