sky130_fd_sc_hd__clkdlybuf4s18

Clock Delay Buffer 4-stage 0.18um length inner stage gates

This is a stub of cell description file

• Cell name: sky130_fd_sc_hd__clkdlybuf4s18

• Type: cell

• Verilog name: sky130_fd_sc_hd__clkdlybuf4s18

• Library: sky130_fd_sc_hd

• Inputs: 1 (A)

• Outputs: 1 (X)

sky130_fd_sc_hd__clkdlybuf4s18 symbols

sky130_fd_sc_hd__clkdlybuf4s18 schematic

sky130_fd_sc_hd__clkdlybuf4s18 GDSII layouts

sky130_fd_sc_hd__clkdlybuf4s18_1

sky130_fd_sc_hd__clkdlybuf4s18_2