sky130_fd_sc_hd__clkdlybuf4s15

Clock Delay Buffer 4-stage 0.15um length inner stage gates

This is a stub of cell description file

• Cell name: sky130_fd_sc_hd__clkdlybuf4s15

• Type: cell

• Verilog name: sky130_fd_sc_hd__clkdlybuf4s15

• Library: sky130_fd_sc_hd

• Inputs: 1 (A)

• Outputs: 1 (X)

sky130_fd_sc_hd__clkdlybuf4s15 symbols

sky130_fd_sc_hd__clkdlybuf4s15 schematic

sky130_fd_sc_hd__clkdlybuf4s15 GDSII layouts

sky130_fd_sc_hd__clkdlybuf4s15_1

sky130_fd_sc_hd__clkdlybuf4s15_2